1. Field of the Invention
The present invention relates to a method for fabricating a chip, and more particularly to a method for fabricating a light emitting diode chip.
2. Description of Related Art
FIGS. 1A through 1F show a fabrication flowchart of a conventional light emitting diode chip. First, a first type semiconductor material layer 122, a light emitting material layer 124 and a second type semiconductor material layer 126 are sequentially formed on a substrate 110 to further form a semiconductor layer 128, as shown by FIG. 1A. A method for forming the semiconductor layer 128 is, for example, a chemical vapor deposition (CVD) process, during which the first type semiconductor material layer 122, the light emitting material layer 124 and the second type semiconductor material layer 126 are sequentially formed on the substrate 110.
Afterwards, the semiconductor layer 128 is patterned to form a semiconductor device layer 120, as shown in FIG. 1B. The semiconductor device layer 120 is formed by a conventional photolithography and etching process (PEP), for example.
Thereafter, a current blocking layer 130 is formed on an upper surface 120a of the semiconductor device layer 120, as shown by FIG. 1C. The current blocking layer 130 is formed by a conventional PEP, for example. To give an example, after a dielectric material layer (not shown) is formed entirely on the substrate 110, the dielectric material layer is patterned to form the current blocking layer 130 as shown by FIG. 1C.
Then, a current spreading layer 140 is formed on the upper surface 120a of the semiconductor device layer 120 to cover the current blocking layer 130, as shown by FIG. 1D. The current spreading layer 140 is formed by a conventional PEP, for example. To give an example, a conductive layer (not shown) is first formed entirely on the substrate 110 to cover the semiconductor device layer 120 and the current blocking layer 130. Next, the conductive layer is patterned to form the current spreading layer 140, as shown by FIG. 1D.
After the foregoing steps are completed, a plurality of electrodes 150 is formed on the current spreading layer 140 and the semiconductor device layer 120, as shown by FIG. 1E. The electrodes 150 are formed by a conventional PEP, for example. To give an example, an electrode material layer (not shown) is formed entirely on the current spreading layer 140 and the semiconductor device layer 120. Next, the electrode material layer is patterned to form the plurality of electrodes 150 on the current spreading layer 140 and the semiconductor device layer 120, as shown by FIG. 1E.
Then, a passivation layer 160 is formed on the current spreading layer 140 and the semiconductor device layer 120 which are not covered by the electrodes 150, as shown by FIG. 1F. The passivation layer 160 is formed by a conventional PEP, for example. To give an example, a dielectric material layer (not shown) is formed entirely to cover the current spreading layer 140, the electrodes 150 and the semiconductor device layer 120. Then, the dielectric material layer is patterned to form the passivation layer 160 on the current spreading layer 140 and the semiconductor device layer 120 which are not covered by the electrodes 150, as shown by FIG. 1F. So far, the process steps of the conventional light emitting diode chip 100 are generally completed.
In view of the foregoing, the method for fabricating the conventional light emitting diode chip 100 performs at least five mask processes to form a plurality of components respectively, such as the semiconductor device layer 120, the current blocking layer 130, the current spreading layer 140, the electrodes 150 and the passivation layer 160. Thus, the light emitting diode chip 100, which requires at least five mask photo processes to fabricate, needs to use a plurality of masks having different patterns. Since each of the masks is rather costly, the fabrication cost and the fabrication time of the light emitting diode chip 100 cannot be reduced.